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NEXTMOVEFDE careers · United States
Cadence Design Systems

Principal AI Forward Deployment Engineer

AI summary of the role

Cadence is hiring a Principal AI Forward Deployment Engineer to embed with strategic semiconductor customers and operationalize Cadence's AI and agentic solutions across their end-to-end silicon design flows.

What you’ll do

  • Lead end-to-end deployment of Cadence AI / LLM-powered solutions into the customer's silicon design flows - from RTL design and verification through synthesis, place-and-route, timing, power, signoff, and packaging.
  • Architect and tune agentic workflows, prompt strategies, RAG pipelines, and tool-calling patterns on top of flagship LLMs (Claude, GPT, Gemini, Llama, Qwen, etc.) to automate real EDA tasks.
  • Map customer methodology (FE design, DV, PD, CAD, signoff) onto Cadence AI building blocks; identify the highest-ROI insertion points; build reference flows the customer's CAD/methodology team can own long-term.
  • Define and report KPIs - cycle-time reduction, engineer-hours saved, iteration count, first-pass success, license/compute efficiency. Own the story from pilot to production rollout across BUs and sites.

What you’ll bring

  • BS/MS/PhD in EE, ECE, CS, or related discipline.
  • 10+ years of hands-on semiconductor / chip design experience in front-end design, physical design, CAD/methodology, or design execution on production tape-outs.
  • Deep, practitioner-level fluency with industry EDA flows and pain points - you have personally shipped silicon.
  • Demonstrated ability to apply LLMs / AI tools to get real engineering work done (e.g., agent-based debug, code/RTL generation assist, scripted automation, copilots, RAG over design docs/logs).

Technologies

LLM · Claude · GPT · Gemini · Llama · Qwen · RAG · AgentStack · Cerebrus · Verisium · Allegro X AI · JEDAI

About Cadence Design Systems

Provides EDA software, hardware emulation, design IP, and multiphysics simulation that semiconductor and systems companies use to design and verify chips, boards, and full electronic systems.

Public · 5000+ people

Source and classification

Production engineering · Evidence for this classification:

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Role Summary Cadence is hiring a Principal AI Forward Deployment Engineer to embed with strategic semiconductor customers and operationalize Cadence's AI and agentic solutions across their end-to-end silicon design flows. This is a senior, customer-facing applied-AI role for an experienced chip-design practitioner who can translate front-end, physical-design, and methodology workflows into concrete, measurable productivity wins powered by flagship LLMs and Cadence AI tooling. You will be the trusted technical lead at the customer who turns 'AI for chip design' from a slideware promise into a deployed, adopted, and ROI-positive reality. Why This Role Exists Customers are racing to apply LLMs and agentic AI to RTL, verification, implementation, and signoff - but they need a
More from the job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Role Summary Cadence is hiring a Principal AI Forward Deployment Engineer to embed with strategic semiconductor customers and operationalize Cadence's AI and agentic solutions across their end-to-end silicon design flows. This is a senior, customer-facing applied-AI role for an experienced chip-design practitioner who can translate front-end, physical-design, and methodology workflows into concrete, measurable productivity wins powered by flagship LLMs and Cadence AI tooling. You will be the trusted technical lead at the customer who turns 'AI for chip design' from a slideware promise into a deployed, adopted, and ROI-positive reality. Why This Role Exists Customers are racing to apply LLMs and agentic AI to RTL, verification, implementation, and signoff - but they need a partner who deeply understands *both* their tape-out flows and how to wield modern AI systems. This role owns the last mile: taking Cadence AI products (AgentStack, BU Super-Agents, Cadence.AI / JEDAI platform, Cerebrus, Verisium, Allegro X AI, etc.) and making them work inside the customer's actual methodology, PDKs, compute fabric, and security boundaries. Success here directly accelerates customer tape-outs, expands Cadence AI footprint, and feeds product roadmaps with real-world signal. What [... source excerpt omitted ...] asks - debug triage, constraint authoring, ECO loops, PD recipe tuning, methodology Q&A, log/report summarization, and design-review copilots. Methodology & Flow Integration. Map customer methodology (FE design, DV, PD, CAD, signoff) onto Cadence AI building blocks; identify the highest-ROI insertion points; build reference flows the customer's CAD/methodology team can own long-term. Productivity & ROI Ownership. Define and report KPIs - cycle-time reduction, engineer-hours saved, iteration count, first-pass success, license/compute efficiency. Own the story from pilot to production rollout across BUs and sites. Trusted Technical Advisor. Be the senior technical face to custom [... source excerpt omitted ...] technical readouts, and joint roadmaps. Translate customer pain into actionable feedback for Cadence R&D and AI platform teams. AI Systems Enablement (plus). Where needed, guide customer IT/InfoSec on secure LLM access patterns, on-prem vs. gateway deployment, model routing, prompt/response logging, data-egress controls, and GPU/inference capacity planning. Knowledge Multiplier. Capture playbooks, reference designs, and 'golden prompts' so every deployment compounds. Mentor field AEs, FAEs, and customer champions. Must-Have Qualifications BS/MS/PhD in EE, ECE, CS, or related discipline. 10+ years of hands-on semiconductor / chip design experience in one or more of: front-en

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