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NEXTMOVEFDE careers · United States

Senior System Software Engineer, RTL-to-GDS Flow Platform

AI summary of the role

NVIDIA seeks a senior flow/platform engineer to build and modernize the production RTL-to-GDS flow infrastructure supporting 1000+ chip design engineers.

No longer in the current catalog. Last included 2026-09-09. Check the employer’s posting for availability.

What you’ll do

  • Build and modernize production RTL-to-GDS flow infrastructure across synthesis, place-and-route, timing, signoff, ECO, and handoff workflows
  • Extend YAML/configuration systems to model workflow intent, stage contracts, validation markers, generated artifacts, override order, and backward-compatible project behavior
  • Improve Make, Perl, Tcl, Python, and related launch infrastructure for generated runsets, EDA tool setup, distributed execution, status tracking, and failure diagnosis
  • Build faster prelaunch and in-run checks for missing inputs, stale generated files, invalid hooks, broken environment setup, bad constraints, and inconsistent design state

What you’ll bring

  • 12+ years building, modernizing, or operating production EDA, VLSI CAD, RTL-to-GDS, physical design, or large engineering workflow systems
  • Strong hands-on experience with RTL-to-GDS or implementation flows, including setup, generated collateral, tool launch, checks, timing/signoff handoff, and debug workflows
  • Strong Tcl and Make experience in real EDA automation environments, plus practical software engineering skill in Python, Perl, Go, or C++
  • Ability to reason about layered configuration, includes, overrides, variable expansion, generated outputs, validation state, and compatibility with older projects

Technologies

RTL-to-GDS · Tcl · Make · Perl · YAML · Python · Go · C++ · LSF · Slurm · Grid Engine · NFS

About NVIDIA

Designs and manufactures GPUs and system-on-chips powering data centers, AI workloads, gaming, autonomous vehicles, and HPC. The foundational hardware for modern deep learning.

Public

Source and classification

Internal deployment & tooling · Evidence for this classification:

The VLSI Productivity and Infrastructure team supports 1000+ chip design engineers with strong automation and workflows necessary to create world-changing silicon. We are building the next generation of production semiconductor design-flow infrastructure: a control-plane-driven RTL-to-GDS platform that turns design intent, configuration, generated collateral, EDA tool execution, distributed jobs, validation checks, and shared project state into observable, repeatable implementation workflows. This role is for a senior flow/platform engineer who can work across synthesis, physical design, timing, signoff, ECO, and hierarchical execution. If you can envision and evolve legacy Tcl/Make/Perl/YAML infrastructure into a cleaner, more structured system while keeping active projects running, this role is for you! What You'll Be Doing: Build and modernize production RTL-to-GDS flow
More from the job description

The VLSI Productivity and Infrastructure team supports 1000+ chip design engineers with strong automation and workflows necessary to create world-changing silicon. We are building the next generation of production semiconductor design-flow infrastructure: a control-plane-driven RTL-to-GDS platform that turns design intent, configuration, generated collateral, EDA tool execution, distributed jobs, validation checks, and shared project state into observable, repeatable implementation workflows. This role is for a senior flow/platform engineer who can work across synthesis, physical design, timing, signoff, ECO, and hierarchical execution. If you can envision and evolve legacy Tcl/Make/Perl/YAML infrastructure into a cleaner, more structured system while keeping active projects running, this role is for you! What You'll Be Doing: Build and modernize production RTL-to-GDS flow infrastructure across synthesis, place-and-route, timing, signoff, ECO, and handoff workflows Extend YAML/configuration systems to model workflow intent, stage contracts, validation markers, generated artifacts, override order, and backward-compatible project behavior Improve Make, Perl, Tcl, Python, and related launch infrastructure for generated runsets, EDA tool setup, distributed execution, status tracking, and failure diagnosis Build faster prelaunch and in-run checks for missing inputs, stale gene [... source excerpt omitted ...] hedulers, generated collateral, and configuration layers What We Need To See: B.S. or M.S. in CS, EE, CE, or equivalent experience 12+ years building, modernizing, or operating production EDA, VLSI CAD, RTL-to-GDS, physical design, or large engineering workflow systems Strong hands-on experience with RTL-to-GDS or implementation flows, including setup, generated collateral, tool launch, checks, timing/signoff handoff, and debug workflows Strong Tcl and Make experience in real EDA automation environments, plus practical software engineering skill in Python, Perl, Go, or C++ Ability to reason about layered configuration, includes, overrides, variable expansion, generated output [... source excerpt omitted ...] Excellent Linux debugging fundamentals and a track record of improving legacy production systems without breaking active users Ways To Stand Out From The Crowd: Background with production flows using commercial synthesis, place-and-route, timing, extraction, DRC/LVS, power, or signoff tools Experience designing workflow engines, runset generators, configuration systems, template-driven automation, or job-control infrastructure Background with distributed schedulers and shared compute environments such as LSF, Slurm, Grid Engine, or similar systems Experience with NFS-heavy shared filesystems, stale state, partial writes, generated input files, provenance tracking, and reprodu

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