Applied ML – Functional Verification Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Position Overview We are seeking a results driven Pre-Silicon Verification Engineer with extensive experience in function verification (formal verification and/or simulation/UVM verification) and a passion for leveraging artificial intelligence to redefine the verification landscape. In this role, you will operate at the forefront of semiconductor design and AI innovation, utilizing advanced AI tools to architect, design, and validate the next generation of verification methodologies. You will collaborate closely with a highly skilled team of machine learning engineers experienced in training large language models at [... source excerpt omitted ...] ies chips with up to 10× productivity gains. Cadence has been nominated as a Great Place to Work globally and in Brazil, and is also a Fortune 100 Best Companies to Work For. Key Responsibilities Contribute to the application of machine learning techniques aimed at streamlining traditional pre-silicon functional verification methodologies like formal verification and UVM. Develop agentic AI solutions using LLMs and latest ML technologies to accelerate pre-silicon Design Verification process. Employ AI enhanced Electronic Design Automation (EDA) tools to improve and expedite both the design and verification lifecycles. Engage directly with customers to understand requirements and [... source excerpt omitted ...] efficiency, and quality. Maintain current knowledge of advancements in AI-powered hardware verification and actively participate in fostering internal knowledge growth. Required Qualifications BS with a minimum of 10 years of experience OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience Proven expertise of more than 3 years in at least one of the pre-silicon ASIC verification methodologies such as Formal, SV/UVM and/or OVM. Advanced skills in debugging pre-silicon verification failures using waveform viewers and simulation analysis tools. Hands-on experience with industry standard EDA tools (e.g., Jasper, Xcelium, IMC). Strong programmin