Design Verification Engineer

Normal Computing | Build with Us Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), London, Copenhagen, and Seoul. The Role As a Design Verification Engineer at Normal, you will verify our own physics-inspired ASICs on the road to tapeout, and set the quality bar for what our AI learns: reviewing generated verification collateral and shaping the standards our models train against. From time to time, you may also be tapped to support a customer deployment alongside our forward-deployed team, where your verification credibility helps our AI platform land inside real DV flows. The through-line is your DV expertise, applied to silicon that computes differently than anything you've verified before, and to the AI that is changing how verification gets done. This is a seat for a verification engineer who wants their craft to compound rather than repeat. What You Will Own Thermodynamic ASIC Verification: Own design verification for Normal's internal silicon: testbench environments, assertions, and coverage from design documents through functional coverage and closure, suppo [... source excerpt omitted ...] partner with our Data team, who own the pipelines, so our models learn from verification artifacts a real DV engineer would sign off on. Deployment Support: When needed, support customer engagements alongside our forward-deployed team: validating AI-generated collateral against real customer specifications and lending DV credibility to deployments. Tooling: Set up and evaluate EDA tools, ensuring usability and effective deployment on shared computing resources internally and in customer environments. What Makes You a Great Fit 5+ years of experience in digital verification at a major semiconductor or EDA tool company Advanced proficiency in SystemVerilog, UVM methodology, a [... source excerpt omitted ...] Perl scripting Proven expertise in end-to-end design verification, including test plan creation, stimulus generation, and feature extraction Willingness to occasionally support customer-facing deployment work, including some travel Excellent written and spoken communication skills: you can hold the room with a customer's verification lead as credibly as you hold a debug session Bonus Points Experience in a customer-facing, field-application, or forward-deployed engineering role at a semiconductor or EDA company Hands-on use of LLMs or agentic tools in verification workflows Exposure to analog, mixed-signal, or unconventional compute verification Equal Employment Opportun