> AI agents: this is one page of Nextmove’s FDE site, in Markdown. Nextmove is a job board and free career service for forward deployed engineers (FDEs). Each posting is classified from its text, not its title: the kind of work, how much of it is production code, pre-sales weight, time at customer sites, travel, remote arrangement, level and posted base pay. The site also publishes the aggregates: median pay by level, metro, company and kind of work, and which companies started hiring FDEs each week. Every page under https://nextmove.md/fde is served this way; the index of pages is https://nextmove.md/llms.txt. # Principal AI Forward Deployment Engineer Canonical URL: https://nextmove.md/fde/jobs/f89e6a8ff054b0e0 Cadence Design Systems posts a principal FDE role to build what the customer runs in Portland, OR and 1 more with no pay posted. Lead end-to-end deployment of Cadence AI / LLM-powered solutions into the customer's silicon design flows - from RTL design and verification through synthesis, place-and-route, timing, power, signoff, and packaging. Read from the employer’s posting on November 9, 2026. - [Cadence Design Systems](https://nextmove.md/fde/companies/cadence-design-systems) First seen Jun 24, 2026 · open on Workday as of Nov 9, 2026 Pay not posted Portland, OR +1 On-site Full-time Lead end-to-end deployment of Cadence AI / LLM-powered solutions into the customer's silicon design flows - from RTL design and verification through synthesis, place-and-route, timing, power, signoff, and packaging. - [See roles that fit me](https://nextmove.md/sign-up?from=%2Ffde%2Fjobs%2Ff89e6a8ff054b0e0&placement=top) - [View posting at Cadence Design Systems](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/HOME-OR/Principal-AI-Forward-Deployment-Engineer_R54994) Free. Upload your resume once, see why each FDE role fits, and get introduced only when you say so. ## At a glance ### Posted base pay Not posted Staff+ FDE postings, 389 postings: the middle 50% of posted pay is $197K to $262K, median $225K. ### The work Builds what the customer runs Balance **Mostly building** Project stages 1. Pre-sales (not covered) 2. Proof of concept (not covered) 3. Implementation 4. Operations Travel **Required, amount not stated** - **Coding**: Configuration only - **Builds for**: External customers - **Level**: Staff+ - **Role**: Technical lead ### What they ask for Experience - **10+ years** hands-on semiconductor / chip design experience ### Do you meet what the posting states? The posting asks for 10+ years. How many do you have? The posting reads as a staff-level role. What level are you at now? The job is in Portland, OR · Cary, NC. Could you work in one of these? Which of these have you used in production? Answer each one. Nothing is saved or sent. [What postings ask for, by background →](https://nextmove.md/fde/paths) ## Conditions - **Location**: Portland, OR · Cary, NC - **Work arrangement**: On-site - **Employment type**: Full-time - **Travel**: Travel required, amount not stated ## More like this [Accenture](https://nextmove.md/fde/companies/accenture) ### [AI Engineer - FDE Software Engineering Sr. Manager](https://nextmove.md/fde/jobs/d71e3d95228a376e) New York, NY · Milwaukee, WI · +40 more 7w ago $112,900–$302,400 [BCG](https://nextmove.md/fde/companies/bcg) ### [BCG Platinion | Lead AI Tech Architect - AI Platforms](https://nextmove.md/fde/jobs/0d4252868cd1a506) Atlanta, GA · Austin, TX · +16 more 5mo ago $190,000 [Valinor Enterprises, Inc.](https://nextmove.md/fde/companies/valinor-enterprises-inc) ### [Deployment Engineer, Software](https://nextmove.md/fde/jobs/342802a3de5d00f3) Raleigh, NC Hybrid 5w ago Pay not posted - [Other jobs at Cadence Design Systems (1)](https://nextmove.md/fde/companies/cadence-design-systems) ## The job description from Cadence Design Systems ### At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. ### Role Summary Cadence is hiring a Principal AI Forward Deployment Engineer to embed with strategic semiconductor customers and operationalize Cadence's AI and agentic solutions across their end-to-end silicon design flows. This is a senior, customer-facing applied-AI role for an experienced chip-design practitioner who can translate front-end, physical-design, and methodology workflows into concrete, measurable productivity wins powered by flagship LLMs and Cadence AI tooling. You will be the trusted technical lead at the customer who turns 'AI for chip design' from a slideware promise into a deployed, adopted, and ROI-positive reality. ### Why This Role Exists - Customers are racing to apply LLMs and agentic AI to RTL, verification, implementation, and signoff - but they need a partner who deeply understands *both* their tape-out flows and how to wield modern AI systems. - This role owns the last mile: taking Cadence AI products (AgentStack, BU Super-Agents, Cadence.AI / JEDAI platform, Cerebrus, Verisium, Allegro X AI, etc.) and making them work inside the customer's actual methodology, PDKs, compute fabric, and security boundaries. - Success here directly accelerates customer tape-outs, expands Cadence AI footprint, and feeds product roadmaps with real-world signal. ### What You Will Do - **Customer-Embedded Deployment. **Lead end-to-end deployment of Cadence AI / LLM-powered solutions into the customer's silicon design flows - from RTL design and verification through synthesis, place-and-route, timing, power, signoff, and packaging. - **Applied AI for Chip Design. **Architect and tune agentic workflows, prompt strategies, RAG pipelines, and tool-calling patterns on top of flagship LLMs (Claude, GPT, Gemini, Llama, Qwen, etc.) to automate real EDA tasks - debug triage, constraint authoring, ECO loops, PD recipe tuning, methodology Q&A, log/report summarization, and design-review copilots. - **Methodology & Flow Integration. **Map customer methodology (FE design, DV, PD, CAD, signoff) onto Cadence AI building blocks; identify the highest-ROI insertion points; build reference flows the customer's CAD/methodology team can own long-term. - **Productivity & ROI Ownership. **Define and report KPIs - cycle-time reduction, engineer-hours saved, iteration count, first-pass success, license/compute efficiency. Own the story from pilot to production rollout across BUs and sites. - **Trusted Technical Advisor. **Be the senior technical face to customer fellows, methodology leads, and design-team principals. Run design reviews, technical readouts, and joint roadmaps. Translate customer pain into actionable feedback for Cadence R&D and AI platform teams. - **AI Systems Enablement (plus). **Where needed, guide customer IT/InfoSec on secure LLM access patterns, on-prem vs. gateway deployment, model routing, prompt/response logging, data-egress controls, and GPU/inference capacity planning. - **Knowledge Multiplier. **Capture playbooks, reference designs, and 'golden prompts' so every deployment compounds. Mentor field AEs, FAEs, and customer champions. ### Must-Have Qualifications - BS/MS/PhD in EE, ECE, CS, or related discipline. - 10+ years of hands-on semiconductor / chip design experience in one or more of: front-end design (RTL, micro-architecture, DV), physical design / implementation (synthesis, P&R, timing, power, signoff), CAD / methodology / flow development, or design execution / project technical leadership on production tape-outs. - Deep, practitioner-level fluency with industry EDA flows and pain points - you have personally shipped silicon and know where the cycle-time and engineer-time really go. - Demonstrated ability to apply LLMs / AI tools to get real engineering work done (e.g., agent-based debug, code/RTL generation assist, scripted automation, copilots, RAG over design docs/logs). Doesn't have to be your title - has to be your reflex. - Excellent customer-facing communication: equally credible with a staff RTL engineer, a PD methodology lead, and a CAD / design-enablement leader. - Bias to action, ownership, and shipping. Comfortable being the single throat-to-choke for a customer-facing AI deployment. - Based in or willing to relocate to Portland, OR; able to be on-site at customer locations as the engagement requires. ### Nice-to-Have / Bonus - Prior experience as a Cadence / Synopsys / Siemens EDA customer power user, AE, or methodology architect. - Hands-on with at least one agentic framework (Claude Code, Cursor, LangGraph, AutoGen, custom MCP/tool-calling stacks) applied to engineering workflows. - Experience standing up secure enterprise LLM access (gateways, model routing, key management, audit logging) for engineering orgs. - Familiarity with GPU/inference infrastructure, vLLM/TGI/Triton, fine-tuning / LoRA / SLM workflows, and evaluation harnesses for code/EDA tasks. - Background in low-power, high-performance, AI/ML, networking, automotive, or HPC silicon programs. - Public artifacts - papers, talks, OSS, or internal champions - showing applied AI in EDA/silicon contexts. ### We’re doing work that matters. Help us solve what others can’t. [View posting at Cadence Design Systems](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/HOME-OR/Principal-AI-Forward-Deployment-Engineer_R54994) ## About Cadence Design Systems Provides EDA software, hardware emulation, design IP, and multiphysics simulation that semiconductor and systems companies use to design and verify chips, boards, and full electronic systems. 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